The present application hereby claims priority under 35 U.S.C. xc2xa7119 on Korean patent publication number 01-76561 filed Dec. 5, 2001, the entire contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device and a sensing control method, and more particularly, to input/output (I/O) line sensing control in a semiconductor memory device and a sensing control method.
2. Description of the Related Art
In a semiconductor memory device, data in a memory cell is read out by passing through a pair of I/O lines, for example, an I/O line and a complementary I/O line. In a readout operation, a difference between the voltages of the I/O line and the complementary I/O line may be very small. Conventionally, since it is important to stably sense the small voltage difference, a charge transfer pre-sensing technique (CTPS) may be used for sensing the voltage difference.
FIG. 1 illustrates a data path using a conventional CTPS in a semiconductor memory device.
Referring to FIG. 1, a pair of bit lines BL and BLB are connected to memory cells 111 and 112 in a memory cell array 11 and connected to a bit line sense amplifier 13 by passing through a pair of isolation transistors 121 and 122 that are responsive to an isolation control signal ISO. The bit line sense amplifier 13 is connected to a pair of I/O lines FIO and FIOB by passing through a pair of column selection transistors 141 and 142 that are responsive to a column selection control signal CSL.
A first precharge circuit 15 responsive to a first precharge signal FIOP is connected between the pair of I/O lines FIO and FIOB, and the I/O lines FIO and FIOB are connected to a pair of data lines SIO and SIOB by passing through a pair of switch transistors 161 and 162. Second precharge circuits 171 and 172, responsive to a second precharge signal SIOP, are connected to the data lines SIO and SIOB, and the data lines SIO and SIOB are connected to a data line sense amplifier 18. A control transistor 19 responsive to a sense enable signal SAEN is connected to the data line sense amplifier 18.
In the data path using the conventional CTPS, in order to increase the voltage difference between the data lines SIO and SIOB in the sensing operation, the low level of a control signal IOSW must be determined to turn on one of the switch transistors 161 and 162 while turning off the other one. That is, a voltage Vgs1 between the gate and source of the switch transistor 161 has to be equal to or greater than the threshold voltage Vth of the switch transistor 161, and a voltage Vgs2 between the gate and source of the switch transistor 162 has to be smaller than the threshold voltage Vth of the switch transistor 162.
In the opposite case, the voltage Vgs1 between the gate and source of the switch transistor 161 has to be smaller than the threshold voltage Vth of the switch transistor 161, and the voltage Vgs2 between the gate and source of the switch transistor 162 has to be equal to or greater than the threshold voltage Vth of the switch transistor 162.
In the prior art, the low level of the control signal IOSW is generated with a predetermined value in the sensing operation. Consequently, when the threshold voltages Vth of the switch transistors 161 and 162 are varied according to a manufacturing process, the switch transistors 161 and 162 may be simultaneously turned on or off, thereby causing misoperation.
The present invention provides a semiconductor memory device having a more stable input/output (I/O) line sensing technique less dependent on variations of a threshold voltage.
The present invention also provides a sensing control method for more stably performing a sensing operation, less dependent on variations of a threshold voltage.
In an exemplary embodiment, the present invention is directed to a semiconductor memory device that includes a control circuit for controlling a pair of switch transistors connected between a pair of I/O lines and a pair of data lines. The control circuit generates a control signal that turns on one switch transistor while turning off the other switch transistor, and varies the voltage level of the control signal according to variation of the threshold voltage of the switch transistors.
A pair of input/output (I/O) lines transfer a pair of differential signals that are read out from the memory cell array. A first precharge circuit precharges the pair of I/O lines to a first level in response to a first precharge signal and a second precharge circuit precharges the pair of data lines to a second level in response to a second precharge signal. A sense amplifier senses and amplifies the voltages of the pair of data lines.
In another exemplary embodiment, the switch transistors are PMOS transistors, the first level is a power supply voltage level, and the second level is the ground voltage level. In another exemplary embodiment, the control circuit includes a first PMOS transistor in which the power supply voltage is applied to the source, the input signal is applied to the gate, and the control signal is output from the drain, a second PMOS transistor in which the power supply voltage is applied to the source, and the drain of the first PMOS transistor is connected to the gate and drain, an inverter for inverting the input signal, a delay circuit for delaying the output signal of the inverter, a first NMOS transistor in which the drain of the first PMOS transistor is connected to the drain and the output signal of the delay circuit is applied to the gate, and a second PMOS transistor in which the source of the first NMOS transistor is connected to the drain, the input signal is applied to the gate, and the ground voltage is applied to the source.
In another exemplary embodiment, the switch transistors are NMOS transistors, the first level is the ground voltage level, and the second level is the power supply voltage level. In another exemplary embodiment, the control circuit includes a first PMOS transistor in which the power supply voltage is applied to the source and the input signal is applied to the gate, an inverter for inverting the input signal, a delay circuit for delaying the output signal of the inverter, a second PMOS transistor in which the drain of the first PMOS transistor is connected to the source, the output signal of the delay circuit is applied to the gate, and the control signal is output from the drain, a first NMOS transistor in which the drain of the second PMOS transistor is connected to the drain, the input signal is applied to the gate, and the ground voltage is applied to the source, and a second NMOS transistor in which the drain of the second PMOS transistor is connected to the drain and gate, and the ground voltage is applied to the source.
A sensing control method for a semiconductor memory device including a pair of switch transistors connected between a pair of I/O lines and a pair of data lines, the sensing control method comprising generating a control signal having a voltage level which varies according to a variation of the threshold voltage of the pair of switch transistors turning on one of the pair of switch transistors while turning off the other of the pair of switch transistors according to the control signal and sensing a pair of differential signals on the pair of data lines.
In another exemplary embodiment, the present invention is directed to a sensing control method for a semiconductor memory device including a memory cell array, a pair of I/O lines for transferring a pair of differential signals that are read out from the memory cell array, a pair of switch transistors having one electrodes connected to the I/O lines, and a pair of data lines connected to the other electrodes of the switch transistors, where the sensing control method includes precharging the I/O lines to a first level in response to a first precharge signal, precharging the data lines to a second level in response to a second precharge signal, generating a control signal having a voltage level which varies according to variation of the threshold voltage of the switch transistors, turning on one switch transistor while turning off the other switch transistor according to the control signal, and sensing the pair of differential signals on the pair of data lines.
In another exemplary embodiment, the first level is a power supply voltage level in the case that the switch transistors are PMOS transistors. In another exemplary embodiment, generating the control signal includes adjusting the voltage level of the control signal to the power supply voltage level according to the logic low level of the input signal, and adjusting the voltage level of the control signal to a value obtained by subtracting the threshold voltage of the PMOS transistor from the power supply voltage according to the logic high level of the input signal.
In another exemplary embodiment, the first level is the ground voltage level in the case that the switch transistors are NMOS transistors and the second level is the power supply voltage level. In another exemplary embodiment, generating the control signal includes adjusting the voltage level of the control signal to the ground voltage level according to the logic high level of the input signal, and adjusting the voltage level of the control signal to a value obtained by adding the threshold voltage of the NMOS transistor to the ground voltage according to the logic low level of the input signal.